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Program

Date

Time

Session

Presenter

20.03.2024

Day 1

09:00-09:30

09:30-09:45

Registration

Opening session

Pedro Diniz
Arnaldo Oliveira
Iouliia Skliarova

09:45-10:30

Keynote 1:

Machine Learning on FPGAs - Opportunities and Perspectives

Chair: Iouliia Skliarova

Jürgen Teich

10:30-11:00

11:00-12:30

Coffee break

Session 1: Applications 1

Chair: Allen Boston

SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation

 

Open-Source SpMV Multiplication Hardware Accelerator for FPGA-based HPC Systems 

Deep Quantization of Graph Neural Networks with Run-time Hardware-Aware Training

12:30-14:00

Lunch

14:00-15:30

Session 2: Applications 2

Chair: Felipe Muñoz

Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach               

Bridging the Gap in ECG Classification: Integrating Self-Supervised Learning with Human-in-the-Loop Amid Medical Equipment Hardware Constraints

Enabling FPGA and AI Engine Tasks in the HPX Programming Framework for Heterogeneous High-Performance Computing

15:30-16:00

16:00-17:30

Coffee break

Session 3: Design methods

Secure eFPGA Configuration: A System-Level Approach               

 

Graphtoy: Fast Software Simulation of Applications for AMD's AI Engines               

 

A DSL and MLIR Dialect for Streaming and Vectorisation

Chair: Torben Kalkhof

Day 2

21.03.2024

09:15-10:00

Keynote 2:

FPGA design for network security

Chair: Pedro Diniz

10:00-10:30

Coffee break

10:30-12:00

Session 4: Architectures

Nele Mentens

Chair: Olle Hansson

Analysis of Process Variation Within Clock Regions of AMD-Xilinx UltraScale+ Devices               

 

High Performance Connected Components Accelerator for Image Processing in the Edge               

Spectral-Blaze: A High-Performance FFT-based CNN Accelerato

12:00-13:30

Lunch

13:30-15:30

Special Section on Projects (5 papers)

Trusted Computing Architectures for IoT Devices
 
PROACT - Physical Attack Resistance of Cryptographic Algorithms and Circuits with Reduced Time to Market
 
A Flexible Mixed-Mesh FPGA Cluster Architecture for High Speed Computing
 
A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator
 
Exploiting FPGAs and Spiking Neural Networks at the Micro-Edge: The EdgeAI Approach

18:30-22:30

Social event: Boat trip and dinner.

Chair: Jaan Raik

18:30-19:30

Boat trip location:

Royal School Of Languages - Aveiro

https://maps.app.goo.gl/J8PwzSzcW97KWWBh8

19:30-22:30

Dinner location:

Day 3

22.03.2024

09:15-10:00

Keynote 3:

DISCRETION: disruptive secure communications for European Defence

Catarina Bastos

10:00-10:30

10:30-12:00

Coffee break

Session 5: Applications and Architectures

Lidar-based 3D object detection in FPGA with Low Bitwidth Quantization            

 

Cryptographic Security through a Hardware Root of Trust               

 

Clock tree degradation analysis caused by radiation  

 

NEUROSEC: FPGA-Based Neuromorphic Audio Security

12:00-12:15

Closing session

Pedro Diniz

Arnaldo Oliveira

Piedad Brox

Chair: Paolo Meloni

Chair: Piedad Jiménez

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